The present invention relates generally to semiconductor memory devices and, more particularly, the present invention relates to nonvolatile flash semiconductor memory devices.
A claim of priority under 35 U.S.C. § 119 is made to Korean Patent Application No. 2006-82982, filed Aug. 30, 2006, the entire contents of which are hereby incorporated by reference.
Semiconductor memories are widely used in electronic components such as, for example, digital logic circuits and microprocessors. These and other such components may be used in a wide variety of applications ranging from satellite communications to consumer electronics. As demands such as reduction in size and increased operating speed in these applications increase, there is a corresponding demand for features such as high integration density and high frequency of operation from semiconductor devices. There is therefore a need to improve the technologies used in manufacturing semiconductor memories to fulfill such demands.
The semiconductor memory devices are generally classified into volatile memory devices and nonvolatile memory devices. In volatile semiconductor memory devices, information is stored on a temporary basis. This may be done in a number of ways. For example, in a volatile memory device, logical information may be stored by setting a logic condition of a bistable flipflop loop as in a static random access memory (SRAM) or by a capacitive charging effect as in a dynamic random access memory (DRAM.) Furthermore, the volatile semiconductor memory stores and reads data when powered on, but looses the stored data when power is cut off.
On the other hand, the nonvolatile semiconductor memory, such as, for example, MROM, PROM, EPROM, and EEPROM, are able to retain their data even when power supply is cut off. Furthermore, a storage condition in the nonvolatile memory may be designed to be either immutable or re-programmable in accordance with the fabrication techniques used to manufacture the semiconductor memory. Because of their ability, among other things, to retain data in the absence of power, nonvolatile semiconductor memory devices are used in a wide variety of applications. For example, nonvolatile memory devices are used for storing program files and micro-codes in applications such as, for example, computers, aerospace engineering, electronic engineering, communications, and customer electronics.
Among the nonvolatile semiconductor memories, MROM, PROM, and EPROM have features that may make it inconvenient for general users to reprogram these devices. The difficulty in reprogramming these devices lies in the design features of these devices which make it difficult to erase and write date to these devices. On the other hand, an EEPROM can be electrically erased and programmed with data. The ability to electrically erase and program an EEPROM memory makes the EEPROM memory widely popular with general users of electronic devices. Furthermore, flash EEPROMs (hereinafter, referred to as ‘flash memory devices’) can be fabricated with high integration density without compromising their ability to store large amounts of data. This feature makes flash EEPROMs popular as large-capacity auxiliary storage units.
Flash memories are usually divided into NOR type and NAND type flash memories. This distinction is based on the connection pattern between cells and bit lines. Specifically, the NOR flash memory is configured such that one bit line is coupled to two or more cell transistors in parallel. Furthermore, in the NOR flash memory, data is stored by channel hot electron injection and erased by Folwer-Nordheim (F-N) tunneling effect. In contrast, the NAND flash memory is configured such that one bit line is coupled to two or more cell transistors in series. In addition, in the NAND flash memory, data is stored and erased by means of the F-N tunneling effect.
In general, the large power consumption by a NOR flash memory may makes it unsuitable for high density operation. However, NOR flash memory is suitable for high frequency operation. In addition, in response to recent demands for more integrated NOR flash memories, NOR flash memories employing a multi-level cell (MLC) scheme capable of storing multiple data bits in a single memory cell are increasingly being manufactured by flash manufacturers.
FIG. 1 illustrates distribution profiles of threshold voltages for different data stored in flash memory cells using a MLC scheme. Specifically, FIG. 1 shows the distribution profiles of threshold voltages of MLCs, each storing 2 bits, and data values corresponding to the threshold voltages.
For example, in the case where a single data bit is stored in a unit cell of the flash memory, the data of the unit cell may be represented with two distribution profiles of threshold voltages. In particular, one threshold voltage distribution profile corresponds to data ‘0’ and the other threshold voltage distribution profile corresponds to data ‘1’.
On the other hand, in the case where multiple data bits are stored in a unit cell of the flash memory, data stored in the unit cell may be represented by four distribution profiles of threshold voltages. These four distribution profiles correspond to data ‘11’, data ‘10’, data '01, and data ‘00’. Moreover, the data values stored in the unit cell are arranged in the order of ‘11’, ‘10’, ‘01’, and ‘00’. That is, the stored data values are arranged in an ascending order along the threshold voltages. In particular, data ‘11’ corresponds to an erased state from where a programming operation begins. An MLC flash memory device storing multi-bit data in a single memory cell is disclosed in U.S. Pat. No. 6,101,125 entitled ‘ELECTRICAL PROGRAMING MEMORY AND METHOD OF PROGRAMMING’.
FIG. 2 is a flow chart showing a conventional MLC programming method operable in a NOR flash memory device, which is disclosed in detail in U.S. Pat. No. 6,101,125.
Referring to FIG. 2, the MLC programming operation of the NOR flash memory device begins from the erased state ‘11’. The procedure of MLC programming is carried out in the sequence of programming data ‘10’ (S100), program-verifying data ‘10’ (S110), programming data ‘01’ (S120), program-verifying data ‘01’ (S130), programming data ‘00’ (S140), and program-verifying data ‘00’ (S150), in this order. Moreover, the distribution profiles of the threshold voltages must be controlled accurately so as to confine the voltage distributions for each data state in well-defined windows.
In order to control the distribution profile of the threshold voltages, a programming scheme such as an incremental step pulse programming (ISPP) scheme may be used to program data onto the flash memory device. According to the ISPP scheme, a threshold voltage increases by an incremental portion of a program loop or voltage. Therefore, the distribution profiles of threshold voltages can be accurately regulated by setting the incremental portion of the program voltage to be smaller. This may make it possible to ensure sufficient margins between voltage distributions of the data states.
FIGS. 3 and 4 are waveform diagrams showing variations of word line voltages Vpgm and Vvfy and a bulk voltage VBULK that are applied to a flash memory cell during the conventional MLC programming operation.
From FIGS. 2 through 4, it can be seen that the conventional multi-bit programming operation is carried out by alternating programming and program-verifying steps with a stepped-up program voltage. For example, as shown in FIG. 3, after a first program voltage Vpgm10_step1 is applied to conduct a first programming step, a program-verifying step begins with a verifying voltage Vvfy10. Thereafter, a second program voltage Vpgm10_step2 is applied to conduct a second programming step and then another program-verifying step begins with the verifying voltage Vvfy10. As seen in FIGS. 3 and 4, the verifying voltage Vvfy10 is higher than the program voltages Vpgm10_step1 and Vpgm10_step2.
Generally, in the conventional multi-bit programming mode where the program voltages (e.g., Vpgm10_step1, Vpgm10_step2, and so on) alternate with the verifying voltage (e.g., Vvfy10), there is a need to have recovery and setup periods. These recovery and set up periods are needed to rapidly change voltage levels when moving from a programming step to a program verifying step and vice versa. As the number of programming steps increase, there is a corresponding increase in the number of recovery and set up periods. In addition, with an increase in the number of recovery and set up periods, there is also an increase in a programming time for the memory cell. Furthermore, there may also be inadvertent overshooting of the program and/or program-verify voltages.
There is therefore a need to develop a programming method and system for programming a flash memory cell with a reduced programming time and a reduced overshooting of programming and/or program verifying voltages.
The present disclosure is directed towards overcoming one or more limitations associated with the conventional programming method of a flash memory cell.